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Carbon Nanotubes Are Getting Closer To Making Our Electronic Devices Obsolete

This article is more than 7 years old.

If you've paid attention to news about carbon nanotubes (CNTs) you've heard this before. "CNTs are the greatest thing since . . .", "CNTs are about to revolutionize . . ." When CNTs first burst onto the technology scene in 1991 after a paper published in the journal Nature by Sumio Iijima the future looked so bright that materials scientists just had to wear shades. CNTs were expected to transform the electronics industry through the production of transistors that were much smaller, faster and more efficient than anything that could be achieved with silicon chip technology.

It hasn't worked out that way because there were a number of unforeseen problems in producing CNT-based electronics on an industrial scale. Now, however, those problems are being solved and the CNT revolution promised 25 years ago may be on the horizon.

The type of CNT that is of interest in the electronics industry is a single-walled tube made from a carbon lattice that is one carbon atom thick. The tube has a diameter of 1 nanometer (nm) which is about 1/10,000th the diameter of a human hair.

Carbon and silicon are both semiconductors. However, because of their small size, the number of transistors made from CNTs that can be placed on a chip is much greater than the number (currently in the single-digit billions) that can be placed on a silicon chip.

CNT chips are not only smaller, they're faster, more efficient and they generate much less heat than silicon chips. In other words, CNT chips would give you lightening speed and much longer battery life without overheating and the need for fans to dissipate excess heat. It's easy to see why people were excited when Iijima published his paper.

Theoretically, integrated circuits made from CNTS are a vast improvement over silicon. Practically, there are three problems that have made it difficult to produce CNTs for electronics at an industrial scale.

  1. The mixture problemThere are two types of CNTs that are intermixed when the nanotubes are created. One type is a semiconductor which is what you need for creating integrated circuits. The other type, which is metallic, conducts electricity like a wire and markedly degrades or destroys an integrated circuit's performance. Reliable integrated circuits made from CNTs demand nanotubes that are 100% semiconductors. The problem has been finding a way to separate the metallic CNTs from the semiconductors.
  2. The electrical resistance problemConducting electricity through the connection between the nanotube and the metallic components of an integrated circuit is difficult because electrical resistance increases as the size of the connection decreases. Efficient use of CNTs involves connections on a scale of ten nm or less which results in resistance levels that are too high to be practical. Increasing the size of the connection means placing fewer CNTs on a chip and the advantage of CNTs over silicon disappears. The problem has been finding a way to overcome resistance with connections on a scale of 10 nm or less.
  3. The alignment problem. Today's state-of-the-art computer chips have over seven billion transistors on 14 nanometer chips. Switching from silicon to CNTs allows many more transistors to be placed in the same space. Fitting billions of transistors on a minuscule surface demands precise alignment and spacing of the nanotubes. The problem has been finding ways to reliably achieve this precision layout.

The mixture problem

In April of last year, a team at the University of Illinois developed an inexpensive method for eliminating metallic CNTs from metallic and semiconducting CNT mixtures. They put a sheet of CNTs on a sheet of metal and applied a thin coating of an organic material over the nanotubes. They then sent a low current into the CNT sheet. The metallic nanotubes heated up because they conduct electricity. The semiconducting nanotubes remained cool because they didn't conduct electricity. The heat melted the organic material coating the metallic nanotubes which exposed them to a dry etching process that selectively removed the metallic CNTs leavng the semiconducting CNTs behind.

A different solution for the mixture problem was reported by a team at McMaster University last month. There are a number of methods for isolating metallic CNTs that involve eliminating the semiconducting CNTs by attaching them to electron-rich polymers. The researchers modified an electron rich polymer so that it was electron poor and showed that this simple change reversed the purification process. The metallic CNTs attached to the polymers and were eliminated leaving the semiconducting CNTs behind.

The electrical resistance problem

In October of last year an IBM -led team of researchers reported a solution to the electrical resistance problem. In a typical configuration metal contacts are attached to the top or the sides of the CNT. The team from IBM placed the contacts at the ends of the nanotube. They also joined the nanotube to the metallic components of the integrated circuit with a molybdenum-based carbide.

Intel's current top-of-the-line chips operate at a 14 nm scale and Intel plans to introduce 10 nm chips in 2017. The team from IBM built a CNT transistor that showed no increase in electrical resistance with contact lengths from 300 nm to less than 10 nm.

The alignment problem

In March of 2014 a team at the University of Wisconsin led by Michael Arnold and Gerald Brady developed a technique they called "dose-controlled, floating evaporative self-assembly" that provides a solution to the alignment problem. Here's how it works. A thin rectangular substrate is stood on end in a shallow container of water. Imagine a six-inch ruler sticking up out of a pan of water and you'll have the idea. A small drop of solution containing semiconducting CNTs is dropped into the water near the substrate. The solution spreads out over the surface of the water and the CNTs are deposited across the surface of the substrate where the substrate comes into contact with water's surface.

The thickness of the line of CNTs deposited on the substrate and the density of CNTs within the line are controlled by slowly pulling the substrate out of the water while the CNTs are being deposited. The substrate continues to be slowly raised after there are no more CNTs in the water which results in an empty band on the substrate. When that band has reached the desired thickness, a new drop of CNT solution is added to the water and the sequence is repeated.

This process produces a precisely spaced array of aligned CNTs that can be used in an integrated circuit. We'll see what the team from Wisconsin did with their aligned nanotubes shortly.

Putting it all together

In September of 2013 a research team at Stanford published an article in the journal Nature that described the first working CNT computer. The processor had 178 transistors made from CNTs and was roughly equivalent in processing power to the first processor Intel sold commercially in 1971. The system was crude by today's standards but it was undeniable evidence that computers could be made with CNTs instead of silicon.

Three years later, on September 2nd of this year, the research team at Wisconsin published a paper in the journal Science Advances that described CNT transistors they built using a combination of their technique for solving the alignment problem with techniques that solved the mixture and electrical resistance problems. Their CNT transistors outperformed equivalent state-of-the-art silicon transistors. Before the publication of this paper the superiority of CNTs over silicon had only been demonstrated with theoretical models. The team at Wisconsin brought state-of-the-art performance achieved with CNT transistors from the realm of the theoretical to the realm of the actual.

The creation of carbon nanotube transistors that outperform silicon transistors is a huge step, but it's only a step. We're not going to be using electronic devices with CNT chips anytime in the immediate future. The keyword here is "immediate". On August 31 Fujitsu Semiconductor announced that they are licensing Nantero's CNT-based NRAM memory to appear in their products by the end of 2018.

It is widely thought that advances in processing power based on silicon chips will have gone as far as they can go sometime around the year 2019. With that date in mind, IBM is striving to make viable CNT chips commercially available by 2020. Will they make it? No one knows for sure, but recent advances in overcoming the problems that have held CNT-based integrated circuits back lead you to think that it's well within the realm of possibility.

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